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128M (4Mx16 bit CellularRAM AD-MUX *2 stack) Low Power PSEUDO SRAM

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64M CellularRAM products are high-speed, CMOS pseudo-static random access memory developed for low-power, portable applications. The 64Mb CellularRAM device has a DRAM core organized as 4 Meg x 16 bits. These devices are a variation of the industry-standard Flash control interface, with a multiplexed address/data bus. The multiplexed address and data functionality dramatically reduce the required signal count, and increases read/write bandwidth. For seamless operation on a burst Flash bus, 64M CellularRAM products incorporate a transparent self refresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device READ/WRITE performance. Two user accessible control registers define device operation. The bus configuration register (BCR) defines how the 64M CellularRAM device interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up and can be updated anytime during normal operation. Special attention has been focused on standby current consumption during self refresh. 64M CellularRAM products include two mechanisms to minimize standby current. Partial array refresh (PAR) enables the system to limit refresh to only that part of the DRAM array that contains essential data. Temperature compensated self refresh (TCSR) uses an onchip sensor to adjust the refresh rate to match the device temperature-the refresh rate decreases at lower temperatures to minimize current consumption during standby. Deep power-down (DPD) enables the system to halt the refresh operation altogether when no vital information is stored in the device. The system configurable refresh mechanisms are accessed through the RCR. This 64M CellularRAM specification defines the industry-standard CellularRAM1.5 x16 A/D Mux feature set established by the CellularRAM Workgroup. It includes support for both variable and fixed latency, with three output-device drive-strength settings, a variety of wrap options, and a device ID register (DIDR).

128M (4Mx16 bit CellularRAM AD-MUX *2 stack) Low Power PSEUDO SRAM

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  • Density: 128M (stacked die)
  • Organistation: 8M X16
  • VCC: 1.7v to 1.95v(1.8v)
  • See Datasheet for all other product variations and specifications
Data Sheet


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